The present disclosure generally relates to systems and methods for circuit testing and more particularly to in-circuit testing and modification of programmable integrated circuit devices.
Early generations of circuit testers used a functional testing methodology wherein test signals were applied at various circuit inputs and output signals were monitored at circuit outputs. Such functional testing suffers from at least two limitations. First, it is difficult to formulate thorough and effective test programs suitable for gathering information concerning a variety of circuits designated for test because of the unique nature of individual circuits. Second, fault isolation to a particular element on a printed circuit board or other circuit assembly having many circuit elements requires an accurate operational understanding of the assembled circuit.
These limitations are particularly severe in circuit assemblies that contain sequential data processing circuits (e.g., flip-flops, data buffers, random access memory (RAM), registers, latches, etc.) because the output of the circuit assembly is a function of the state of the circuit, as well as of the applied test (i.e., data) signals. In order to know the state of a circuit with sequential elements, it is generally necessary to apply a set of signals to the inputs of the circuit""s sequential elements, which alter each individual element""s state until it enters a desired state known as its xe2x80x9chomexe2x80x9d state. The application of the required signals that result in a particular sequential circuit element reaching its xe2x80x9chomexe2x80x9d state is known as xe2x80x9choming.xe2x80x9d
The complicated nature of the relationships between test signals applied at circuit inputs and the resulting signals at the inputs of the individual sequential circuit components, makes it extremely difficult to determine the signals that must be applied at the circuit assembly inputs to xe2x80x9chomexe2x80x9d each sequential circuit element in the circuit assembly. As a result of the limitations of functional testing, many circuit assembly testers utilize a technique known as in-circuit testing in which individual circuit components (both sequential and non-sequential) are tested via in-circuit application of test signals at the inputs of each component and concurrent observation of resulting output signals at the various outputs of each component. A description of a typical test program and test equipment that may run the test program is provided below.
For simple circuits, testing is often accomplished by applying appropriate voltages to circuit nodes to test for short or open circuits. Circuit nodes are any equipotential circuit element, such as, but not limited to, connecting wires, edge connectors, and connector pins. Functional testing methods as described above may also be performed where the tester and/or test equipment has sufficient knowledge of circuit operation.
As circuit assemblies become more complex, circuit testers have had to adapt in order to accurately and thoroughly test these complex assemblies. With the added complexity and density due to miniaturization, it has become more important, and more difficult, to thoroughly test circuit assemblies.
Many of today""s circuit assembly manufacturers develop circuit assembly test methods concurrently with the development of the circuit assemblies that they are to test. Often, printed circuit cards and individual integrated circuits have one or more test ports integrated with the card or the circuit itself to enable testing of the respective device.
Generally, today""s automated circuit assembly tests include a test program (i.e., a software application) that operates a test interface that communicates various steady-state voltages and test signals between test equipment and the device under test (DUT). The test interfaces may access the various test ports as well as other circuit nodes on the DUT. The test equipment may include numerous resources, such as voltage drivers, receivers, relays, and test pins arranged to engage appropriate locations of the DUT. The drivers and receivers are alternately connected and may be jointly connected in some embodiments (as for bidirectional data busses) in a systematic and clocked sequence to various nodes of the DUT. The drivers and receivers may be connected via relays and test pins that contact various circuit assembly nodes.
In a typical clock period of the test program, drivers will force a first plurality of test pins in contact with DUT nodes to prescribed voltages and check that receivers connected to a second plurality of test pins in contact with other DUT nodes receive anticipated output signals. If, at any clock cycle in the sequence, the anticipated output signals are not observed, the DUT may be deemed defective. Test abnormalities may be recorded or otherwise indicated by the test equipment. Upon encountering an abnormal result the test may be terminated or the test program may execute steps in an effort to isolate and identify the cause of the abnormal result.
The signals transmitted and received during a test can be viewed as a large matrix of data: the columns of the matrix being associated with a test pin, and the rows of the matrix corresponding to a test vector at a given clock cycle. The matrix is stored and communicated to the test equipment during the test. Generally, the matrix is stored on a non-volatile storage element such as, but not limited to, a magnetic disk or tape. The matrix may then be loaded into a random access memory element as needed to perform the test. The xe2x80x9cflattenedxe2x80x9d or xe2x80x9cunrolledxe2x80x9d form of the matrix includes test vectors for each clock cycle of the test program. A test vector is the set of signals transmitted to and/or received from the test pins on a given clock cycle.
Storing and using this flattened or unrolled form of the matrix is memory intensive and expensive. Consequently, some systems store the matrix of test vectors in a compressed form. For example, U.S. Pat. No. 4,652,814 describes a system that stores unique test vectors in test equipment memory elements. The system associates a local test data RAM, which contains both stimulus and response data for use at an associated test pin. The stimulus and response data is compressed to reduce the amount of data that is downloaded to perform a particular test. The system apparently described in the ""814 patent uses a sequencer that applies the unique test vectors in an order defined by various subroutines, loops, etc. in the test program. During a test, the sequencer forwards the test vectors in the appropriate order to the appropriate pin locations, thus constructing the flattened form of the test from the compressed data.
As electronic devices have become more and more complex, the number of input and output pins associated with individual integrated circuits used in the devices has increased. Consequently, the number of test pins required to test individual on-board integrated circuits and the associated host circuit assemblies has grown commensurately. As the number of test pins, and thus the size of the test vector, becomes large, not only does the test matrix grow the test matrix becomes increasingly difficult to compress.
The compression becomes more difficult because the compression methods attempt to identify sections of a test that are repeated and thus reusable. For example, a sequence of test vectors A-B-C may recur often in a test, and compression methodologies can take advantage of the repetition by storing A-B-C once, and reusing the sequence during the test. However, as test vectors become larger, the chance that a particular sequence of test vectors recurs decreases.
As a result, ever increasing amounts of data must be communicated to the pin electronics (i.e., the various drivers and receivers associated with each of a plurality of test pins that form the physical interface between an in-circuit tester and a DUT) in a testing device in order to thoroughly test both the integrated circuit assemblies and the individual components mounted on the assembly. In addition, manufacturers of devices that use integrated circuit assemblies with programmable integrated circuits have found it desirable from manufacturing and handling perspectives to create application programs that combine the data necessary to program on-board integrated circuits with a test program. The composite application programs can then be used to program and/or otherwise configure the individual programmable devices prior to testing the individual integrated circuit and/or the host circuit assembly.
The combination of the on-board programming information with the test data further increases the data storage capacity required to test today""s complex circuit assemblies. Consequently, it is often the case that the amount of data that must be transferred to the test equipment in order to both program the various programmable devices and to thoroughly test the circuit assembly exceeds the storage capacity of the test equipment.
One known method of addressing the problem of insufficient storage space in the test equipment is to divide the application program into a plurality of test and/or program segments. As long as the resulting segments do not separately exceed the storage capacity of the test equipment, the segments can be run separately. However, between each segment, the test sequencer must be paused and the test memory element must be reloaded with the new data. The application program can then be restarted after the next segment has been successfully loaded in the test memory element. While this segmenting approach is functional, its use results in undesirable complexity in developing the segmented tests and delays in the serial programming and testing of mass-produced circuit assemblies due to the need to pause the circuit tester to reload memory elements.
Another known method of addressing the problem of insufficient storage space in the test equipment is to increase the storage capacity of the test memory device. While commercially available RAM devices may provide increased storage capacity over time, each generation is often accompanied by a change in the number of pins and/or interfaces to the device. Furthermore, integrated circuit RAM devices with the storage capacities required to store both the test program and data required to program on-board programmable devices are more expensive than smaller capacity RAM devices. Because test and programming data requirements are expected to grow at a rapid rate, alternative systems and methods are desired to address the insufficient storage capacity and inherently poor data throughput in circuit assembly test and programming devices.
In response to these and other shortcomings of the prior art, systems and methods for increasing the data throughput and data capacity of digital circuit testers are disclosed. Briefly described, in architecture, an improved circuit tester can be realized with a data accelerator for use in a test vector sequencer. The data accelerator may comprise a data translator, a plurality of sequence memory devices, and a switch. In preferred embodiments, the data translator and the switch are configured via a single control signal responsive to an indication that a first sequence memory device is prepared to receive a data segment and that a second sequence memory device is prepared to simultaneously transfer a previously stored data segment.
Some embodiments of the improved circuit tester can be viewed as providing methods for increasing data throughput. In this regard, a method for increasing data throughput can be summarized by the following steps: a) segmenting a test application into a plurality of application segments; b) acquiring a first application segment in a first test sequencer storage device; c) configuring the test sequencer to forward the first application segment to program or test a circuit and to simultaneously acquire a subsequent application segment in a second test sequencer storage device; d) detecting a condition responsive to the completion of an application segment transfer associated with both the first and second test sequencer storage devices; e) reconfiguring the test sequencer to forward the subsequent application segment and to simultaneously acquire a further subsequent application segment in the first test sequencer storage device; and f) repeating the configuring, forwarding, and detecting steps until the last of the plurality of application segments have been forwarded.
Other systems, methods, and features associated with the improved circuit tester will become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, and features included within this description, be within the scope of the system and method for increased data throughput and data capacity as protected by the accompanying claims.